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KS57C3316/p3316 product overview 1- 1 1 product overview overview the KS57C3316 single-chip cmos microcontroller has been designed for high perfo rmance using samsung's newest 4- bit cpu core, sam47 (samsung arrangeable microcontrollers). with features such as lcd direct drive capability, 4-channel a/d converter, 8-bit timer/counter, watch timer and pll frequency synthesizer, it offers you an excellent design solution for a wide variety of applications that require lcd functions and audio applications . up to 56 pins of the 80 -pin qfp package , it can be dedicated to i/o. eight vectored interrupts provide fast response to internal and external events. in addition, the KS57C3316 's advanced cmos technology provides for low power consumption and a wide operat ing voltage range. otp the KS57C3316 microcontroller is also available in otp (one time programmable) version, ks57p3316. the ks57p3316 microcontroller has an on-chip 16-kbyte one-time-programmable eprom instead of masked rom. the ks57p3316 is comparable to KS57C3316, both in function and in pin configuration.
product overview KS57C3316/p3316 1- 2 features memory 512-nibble ram 16k-byte rom i/o pins input only: 4 pins output only: 28 pins i/o: 24 pins lcd controller/driver maximum 14-digit lcd dire ct drive capability 28 segment x 4 common signals display modes: static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-bit basic timer programmable interval timer functions watch-dog timer function 8-bit timer /counter programmable 8-bit timer external event counter arbitrary clock frequency output external clock signal divider serial i/o interface clock generator watch timer time interval generation : 0.5 s, 3.9 ms at 32.768 khz f requency outputs to buz pin clock source generation for lcd 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode data direction selectable (lsb-first or msb-first) internal or external clock source a/d converter 4-channels with 8-bit resolution bit sequential carrier buffer support 16-bit serial data transfer in arbitrary format pll frequency synthesizer level = 300 mvp-p (min) amvco range = 0.5 mhz to 30 mhz fmvco range = 30 mhz to 150 mhz 16-bit intermediate frequency (if) counter level = 300 mvp-p (min) amif range = 100 khz to 1 mhz fmif range = 5 mhz to 15 mhz
KS57C3316/p3316 ( preliminary spec ) product overview 1- 3 features ( continued ) interrupts four internal vectored interrupts four external vectored interrupts two quasi-interrupts memory-mapped i/o structure data memory bank 15 t hree power-down modes idle : o nly cpu clock stops stop1: m ain system or subsystem clock stops stop2: m ain system and subsystem clock stop ce low: pll and ifc stop oscillation sources crystal or ceramic oscillator for main system clock crystal for subsystem clock main system clock frequency: 4. 5 mhz ( typ ) subsystem clock frequency: 32.768 k hz ( typ) cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.9, 1. 8 , 1 4.2 m s at 4. 5 mhz 122 m s at 32.768 khz (subsystem) operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v at 3mhz pll/ifc operation: 2.5v to 3.5v or 4.0v to 5.5v package type 80 -pin qfp
product overview KS57C3316/p3316 1- 4 block diagram program status word arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block instruction register clock 16k-byte program memory 512 x 4-bit data memory timer/ counter 0 x in x out program counter i/o port 6 i/o port 5 stack pointer pll synthesizer lcd driver/ controller watchdog timer basic timer a/d converter p5.0/adc0 p5.3/adc3 p5.1/adc1 p5.2/adc2 serial i/o port i/o port 4 i/o port 3 i/o port 2 i/o port 0 output port 7,8,9,10 output port 11,12,13 if counter p4.0/ sck p4.3/clo p4.1/so p4.2/si p3.0 p3.3 p3.1 p3.2 p2.0 p2.3 p2.1 p2.2 p1.0/int0 p1.3/int4 p1.1/int1 p1.2/int2 p10.0-p10.3 /seg12-seg15 p7.0-p7.3 /seg0-seg3 p9.0-p9.3 /seg8-seg11 p8.0-p8.3 /seg4-seg7 p6.0-p6.3 ks0-ks3 p13.0-p13.3 /seg24-seg27 p12.0-p12.3 /seg20-seg23 p11.0-p11.3 /seg16-seg19 bias vlc0-vlc2 com0-com3 vcoam vcofm eo amif fmif ce xt in xt out input port 1 p0.0/btco p0.3/buz p0.1/tclo0 p0.2/tcl0 watch timer int0-int4 figure 1 -1 . KS57C3316 simplified block diagram
KS57C3316/p3316 ( preliminary spec ) product overview 1- 5 pin assignments KS57C3316 (80-qfp-top view) p4.1/so p4.2/si p4.3/clo p5.0/adc0 p5.1/adc1 p5.2/adc2 p5.3/adc3 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 v dd 0 v ss 0 x out x in test xt in xt out reset bias vlc0 vlc1 vlc2 com0 fmif amif v ss 1 vcoam vcofm p2.3 p2.2 p2.1 p2.0 seg27/p13.3 seg26/p13.2 seg25/p13.1 seg24/p13.0 seg23/p12.3 seg22/p12.2 seg21/p12.1 seg20/p12.0 seg19/p11.3 seg18/p11.2 seg17/p11.1 seg16/p11.0 seg15/p10.3 seg14/p10.2 seg13/p10.1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 seg12/p10.0 seg11/p9.3 seg10/p9.2 seg9/p9.1 seg8/p9.0 seg7/p8.3 seg6/p8.2 seg5/p8.1 seg4/p8.0 seg3/p7.3 seg2/p7.2 seg1/p7.1 seg0/p7.0 com3 com2 com1 v dd 1 e0 ce p3.0 p3.1 p3.2 p3.3 p0.0/btco p0.1/tclo0 p0.2/tcl0 p0.3/buz p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p4.0/ sck figure 1 -2 . KS57C3316 80- qfp pin assignment
product overview KS57C3316/p3316 1- 6 pin descriptions table 1 - 1. KS57C3316 pin descriptions pin name pin type description num ber share pin reset value circuit type p 0 .0 p 0. 1 p 0 .2 p 0 .3 i /o 4-bit i/o port. 1-bit or 4-bit read, write, and test are possible. pull-up resistors can be configured by software. 72 73 74 75 btco tclo0 tcl0 buz input d-2 d-2 d-4 d-2 p 1 .0 p1.1 p1.2 p 1 .3 i 4-bit input port. 1-bit or 4-bit read and test are possible. pull-up resistors can be configured by software. 76 77 78 79 int0 int1 int2 int4 input a-4 p 2.0-p2.3 p3. 0-p3.3 i/o 4-bit i/o ports. 1-bit, 4-bit or 8-bit read, write and test are possible. pull-up resistors can be configured by software. ports 2 and 3 can be paired to support 8-bit data transfer. 56-59 68-71 ? input d-2 p4.0 p4.1 p4.2 p4.3 i/o 4-bit i/o ports. 1-bit, 4-bit or 8-bit read, write and test are possible. pull-up resistors can be configured by software. 80 1 2 3 sck so si clo input d-4 d-2 d-4 d-2 p5.0 p5.1 p5.2 p5.3 i/o ports 4 and 5 can be paired to support 8-bit data transfer. 4 5 6 7 adc0 adc1 adc2 adc3 input f-10 p6.0 p6.1 p6.2 p6.3 i/o 4-bit i/o port. 1-bit, 4-bit or 8-bit read, write and test are possible. pull-up resistors can be configured by software. 8 9 10 11 ks0 ks1 ks2 ks3 input d-7 p7.0 p7.1 p7.2 p7.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 28 29 30 31 seg0 seg1 seg2 seg3 output h-28 p8.0 p8.1 p8.2 p8.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 32 33 34 35 seg4 seg5 seg6 seg7 output h-28 p9.0 p9.1 p9.2 p9.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 36 37 38 39 seg8 seg9 seg10 seg11 output h-28 p10.0 p10.1 p10.2 p10.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 40 41 42 43 seg12 seg13 seg14 seg15 output h-28
KS57C3316/p3316 ( preliminary spec ) product overview 1- 7 table 1 - 1. KS57C3316 pin descriptio ns (continued) pin name pin type description num ber share pin reset value circuit type p11.0 p11.1 p11.2 p11.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 44 45 46 47 seg16 seg17 seg18 seg19 output h-28 p12.0 p12.1 p12.2 p12.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 48 49 50 51 seg20 seg21 seg22 seg23 output h-28 p13.0 p13.1 p13.2 p13.3 o 1-bit or 4-bit output port. alternatively used for lcd segment output. 52 53 54 55 seg24 seg25 seg26 seg27 output h-28 com0- com3 o common signal output for lcd display 24-27 ? output h bias i lcd power control 20 ? input ? v lc0 v lc1 v lc2 i lcd power supply. voltage dividing resistors are assignable by software 21 22 23 ? input ? v dd0 ? main power supply 12 ? ? ? v ss0 ? main ground 13 ? ? ? reset i system reset pin 19 ? input b x out x in ? crystal, or ceramic oscillator pin for main system clock. (for external clock input, use x in and input x in ?s reverse phase to x out ) 14 15 ? ? ? xt out xt in ? crystal oscillator pin for subsystem clock. (for external clock input, use xt in and input xt in ?s reverse phase to xt out ) 18 17 ? ? ? test i test signal input (must be connected to v ss for normal operation) 16 ? ? ? ce i input pin for checking device power. normal operation is high level and pll/ifc operation is stopped at low level. 67 ? input b-5 vcofm vcoam i external vcofm/am signal inputs. 60 61 ? input b-4 eo o pll?s phase error output 66 ? output a-2 fmif amif i fm/am intermediate frequency signal inputs. 64 63 input ? b-4 v dd1 ? pll/ifc power supply 65 ? ? ? v ss1 ? pll/ifc ground 62 ? ? ?
product overview KS57C3316/p3316 1- 8 table 1 - 1. KS57C3316 pin descriptio ns (concluded) pin name pin type description num ber share pin reset value circuit type btco i/o basic timer overflow output signal 72 p0.0 input d-2 tclo0 i/o timer/counter 0 clock output signal 73 p0.1 input d-2 tcl0 i/o external clock input for timer/counter 0 74 p0.2 input d-4 buz i/o 2,4,8 or 16 khz frequency output for buzzer sound for 4.19 mhz main system clock or 32.768 khz subsystem clock 75 p0.3 input d-2 int0 int1 i external interrupt. the triggering edges (rising/falling) are selectable. only int0 is synchronized with system clock. 76 77 p1.0 p1.1 input a-4 int2 i quasi-interrupt with detection of rising edge signal. 78 p1.2 int4 i external interrupt input with detection of rising or falling edges. 79 p1.3 sck i/o sio interface clock signal 80 p4.0 input d-4 si i/o sio interface data input signal 1 p4.2 so i/o sio interface data output signal 2 p4.1 clo i/o cpu clock output 3 p4.3 ks0-ks3 i/o quasi-interrupt input with falling edge detection 8-11 p6.0- p6.3 input d-7 adc0- adc3 i/o adc input ports. 4-7 p5.0- p5.3 input f-10 seg0- seg3 o lcd segment signal output. 28-31 p7.0- p7.3 output h-28 seg4- seg27 o lcd segment signal output. 32-55 p8-p13 output h-28
KS57C3316/p3316 ( preliminary spec ) product overview 1- 9 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a out up v dd down p-channel n-channel figure 1 -4 . pin circuit type a-2(eo) in v dd pull-up enable figure 1 -5 . pin circuit type a-4 (p1) schmitt trigger in v dd pull-up resistor figure 1 -6 . pin circuit type b ( reset ) type a n-ch in feedback enable pull-down enable figure 1 -7 . pin circuit type b-4 in figure 1 -8 . pin circuit type b-5(ce)
product overview KS57C3316/p3316 1- 10 p-channel n-channel v dd out output disable data figure 1 -9 . pin circuit type c p-channel i/o output disable data circuit type c pull-up enable v dd figure 1 -10 . pin circuit type d-2 p-channel i/o output disable data circuit type c pull-up enable v dd schmitt trigger figure 1 -11 . pin circuit type d-4 p-channel i/o output disable data circuit type c pull-up enable v dd schmitt trigger port enable figure 1 -12 . pin circuit type d-7 (p6)
KS57C3316/p3316 ( preliminary spec ) product overview 1- 11 pull-up enable circuit type c data output disable adcen to adc data v dd i/o adc select figure1-13. pin circuit type f-10 (p5) out v lc0 v lc1 lcd com v lc2 figure 1-14. pin circuit type h (com0-com3) out v lc0 v lc1 seg v lc2 output disable figure 1-15. pin circuit type h-4 p-ch n-ch v dd output output disable data circuit type h-4 pne n-ch seg figure 1-16. pin circuit type h-28 (p7-p13)
KS57C3316/p3316 ele ctrical data 17- 1 1 7 electrical data overview in this section, information on KS57C3316 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? input timing for reset ? input timing for external interrupts and quasi-interrupts stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
KS57C3316/p3316 ks57 p3316 otp 18- 1 1 8 ks57p3316 otp overview the ks57p3316 single-chip cmos microcontroller is the otp (one time programmable) version of the KS57C3316 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the ks57p3316 is fully compatible with the KS57C3316, both in function and in pin configuration. because of its simple programming requirements, the ks57p3316 is ideal for use as an evaluation chip for the KS57C3316.
ks57p3316 otp KS57C3316/p3316 18- 2 p4.1/so p4.2/si p4.3/clo p5.0/adc0 p5.1/adc1 p5.2/adc2 p5.3/adc3 p6.0/ks0 p6.1/ks1 sdat /p6.2/ks2 sclk /p6.3/ks3 v dd /v dd 0 v ss /v ss 0 x out x in v pp /test xt in xt out reset / reset bias v lc 0 v lc 1 v lc 2 com0 v dd 1 e0 ce p3.0 p3.1 p3.2 p3.3 p0.0/btco p0.1/tclo0 p0.2/tcl0 p0.3/buz p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p4.0/ sck seg12/p10.0 seg11/p9.3 seg10/p9.2 seg9/p9.1 seg8/p9.0 seg7/p8.3 seg6/p8.2 seg5/p8.1 seg4/p8.0 seg3/p7.3 seg2/p7.2 seg1/p7.1 seg0/p7.0 com3 com2 com1 fmif amif v ss 1 vcoam vcofm p2.3 p2.2 p2.1 p2.0 seg27/p13.3 seg26/p13.2 seg25/p13.1 seg24/p13.0 seg23/p12.3 seg22/p12.2 seg21/p12.1 seg20/p12.0 seg19/11.3 seg18/p11.2 seg17/p11.1 seg16/p11.0 seg15/p10.3 seg14/p10.2 seg13/p10.3 ks57p3316 (80-qfp top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 figure 18-1. ks57p3316 pin assignments (80-qfp)
KS57C3316/p3316 ks57 p3316 otp 18- 3 table 18-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p6.2 sdat 10 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input or push-pull output port. p6.3 sclk 11 i/o serial clock pin. input only pin. test v pp (test) 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. reset reset 19 i chip initialization v dd / v ss v dd / v ss 12/13 i logic power supply pin. v dd should be tied to +5 v during programming. table 18-2. comparison of ks57p3316 and KS57C3316 features characteristic ks57p3316 KS57C3316 program memory 16k bytes eprom 16k bytes mask rom operating voltage (v dd ) 1.8 v to 5.5 v 2.5 v to 3.5 v or 4.0 v to 5.5 v at pll/ifc operation 1.8 v to 5.5 v 2.5 v to 3.5 v or 4.0 v to 5.5 v at pll/ifc operation otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 80 qfp 80 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the vpp (test) pin of the ks57p3316, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 18-3. operating mode selection criteria v dd vpp(test) reg/ mem address(a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
ks57p3316 otp KS57C3316/p3316 18- 4 table 18-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below 0.7 v dd ? v dd v v ih2 p0.2, p1, p4.0, p4.2, p5, p6, ce and reset 0.8 v dd v dd v ih3 x in , x out , xt in , and xt out v dd ?0.1 v dd input l ow v oltage v il1 all input pins except those specified below ? ? 0.3 v dd v il2 p0.2, p1, p4.0, p4.2, p5, p6, ce and reset 0.2 v dd v il3 x in , x out , xt in , and xt out 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v , eo; i oh = ? 1 ma v dd ?2.0 ? v dd v oh2 v dd = 4.5 v to 5 . 5 v ; other output ports; i oh = ? 1 ma v dd ?1.0 v dd output low voltage v ol1 v dd = 4.5 v to 5.5 v , eo; i ol = 1 ma , ? ? 2.0 v ol2 v dd = 4.5 v to 5.5 v other output ports; i ol = 10 ma ? ? 2 input h igh leakage c urrent (note) i lih v in = v dd all input pins ? ? 3 m a input low leakage c urrent (note) i lil v in = 0 v all input pins ? ? ? 3 output h igh l eakage c urrent (note) i loh v out = v dd all output pins ? ? 3 output l ow l eakage c urrent (note) i lol v o ut = 0 v all output pins ? ? ? 3 note: except for x in , x out , x t in , and x t out
KS57C3316/p3316 ks57 p3316 otp 18- 5 table 18-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units v lc0 output voltage v lc0 t a = 25 c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2 com output voltage deviation v dc v dd = 5v, (v lc0 - com i i = 0 - 3 ) io = 15 m a (i = 0 - 3) ? 45 120 mv seg output voltage deviation v ds v dd = 5v, (v lc0 - com i i = 0 - 3 ) io = 15 m a (i = 0 - 3) 45 120 lcd output voltage deviation r lcd t a = 25 c 70 100 150 k w oscillator feed back resistors r osc1 v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0 v 300 600 1500 r osc2 v dd = 5.0 v, t a = 25 c xt in = v dd , xt out = 0 v 1500 3000 4500 pull-down resistor r d v dd = 5.0 v, v in = v dd ; vcofm, vcoam, amif, and fmif 15 30 45 pull-up resistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 4, 5, and 6 25 47 100 v dd = 3 v 50 95 200 r l2 v in = 0 v; v dd = 5 v reset 100 220 400 v dd = 3 v 200 450 800
ks57p3316 otp KS57C3316/p3316 18- 6 table 18-4 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd 1 (2) main operating: pcon = 0011b, scmod = 0000b ce = v dd ; crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.5 mhz ? 5.5 27 ma i dd 2 (2) ce low mate: 6.0 mhz ? 3.5 8 pcon = 0011b, scmod = 0000b ce = 0 v crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.5 mhz 2.5 5.5 v dd = 3 v 10% 6.0 mhz 1.6 4 4.5 mhz 1.2 3 i dd 3 ( 2 ) main i dle mode : 6.0 mhz ? 1.0 2.5 pcon = 0111b, scmod =0000b c rystal oscillator c1 = c2 = 22 pf v dd = 5 v 10 % 4.5 mhz 0.9 2.0 v dd = 3 v 10% 6.0 mhz 0.5 1.0 4.5mhz 0.4 0.8 i dd 4 (2) sub operating mode: pcon = 0011b, scmod = 1001b ce = 0 v; v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ua i dd 5 (2) sub i dle mode: pcon = 0111b, scmod = 1001b ce = 0 v; v dd = 3 v 10% 32 khz crystal oscillator ? 6 15 i dd6 (2) stop mode: cpu = fxt/4, scmod = 1101b ce = 0 v; v dd = 5 v 10% ? 0.5 3 i dd 7 (2) stop mode: cpu = fx/4, scmod = 0100b v dd = 5 v 10% ? notes: 1. supply current does not include current drawn through internal pull-up resistors and lcd voltage dividing resistors. 2 . data includes the power consumption for sub - system clock oscillation.
KS57C3316/p3316 ks57 p3316 otp 18- 7 table 18-5 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
ks57p3316 otp KS57C3316/p3316 18- 8 table 18-6 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs.
KS57C3316/p3316 ks57 p3316 otp 18- 9 table 18-7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f clk = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf table 18-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.3 64 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0 ? k s2 10 reset and ce input low width t rsl input 10 1 ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx x as assigned by the imod0 register setting. table 18-8 . a.c. electrical characteristics ( continued) (t a = ? 1 0 c to + 70 c, v dd = 3.5 v to 5 . 5 v) parameter symbol conditions min typ max units a/d converting resolution ? ? ? 8 ? bits absolute accuracy ? ? ? ? 2 lsb ad conversion time t con ? 17 34/fxx (note) ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an v dd = 5 v 2 1000 ? m w note: fxx stands for the system clock ( fx or fxt).
ks57p3316 otp KS57C3316/p3316 18- 10 table 18-8. a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c , v dd = 2.5 v to 3.5 v or v dd = 4.0 v to 5.5 v) parameter symbol conditions min typ max units vcofm, vcoam, fmif and amif input voltage (peak to peak) v in sine wave input 0.3 ? v dd v frequency fv coam vcoam mode, sine wave input; v in = 0.3v p-p 0.5 ? 30 mhz fv cofm vcofm mode, sine wave input; v in = 0.3v p-p 30 150 f amif amif mode, sine wave input; v in = 0.3v p-p 0.1 1.0 f fmif fmif mode, sine wave input; v in = 0.3v p-p 5 15
KS57C3316/p3316 ks57 p3316 otp 18- 11 table 18-8 . a.c. electrical characteristics ( continued) (t a = ? 4 0 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s v dd = 1.8 v to 5.5 v 1.3 ? 64 with subsystem clock ( fxt) 114 122 125 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 tcl0 input high, low width t tih , t til v dd = 2.7. v to 5.5 v 0.48 ? ? m s v dd = 1.8. v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 650 v dd = 1.8 v to 5.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v external sck source 400 ? ? internal sck source t kcy /2- 50 v dd = 1.8 v to 5.5 v external sck source 1600 internal sck source t kcy /2-150 si setup time to t sik external sck source 100 ? ? sck high internal sck source 150 si hold time to t ksi external sck source 400 ? ? sck high internal sck source 400 output delay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 note: u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source.
ks57p3316 otp KS57C3316/p3316 18- 12 1.5 mhz cpu clock 750 khz 15.6 khz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 250 khz 1.0475 mhz 1 mhz when pll/ifc operation, operating voltage range is 2.5 v to 3.5 v or 4.0 v to 5.5 v. main oscillator frequency 6 mhz 4.19 mhz 3 mhz 400 khz figure 18-2 . standard operating voltage range table 18-9 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 1 m a
KS57C3316/p3316 ks57 p3316 otp 18- 13 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 18-3 . stop mode release timing when initiated b y reset execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 18-4 . stop mode release timing when initiated b y an interrupt request
ks57p3316 otp KS57C3316/p3316 18- 14 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 18-5 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 18-6 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 18-7 . clock timing measurement at xt in
KS57C3316/p3316 ks57 p3316 otp 18- 15 reset t rsl 0.2 v dd figure 18-8 . input timing for reset signal int0, 1, 2, 4, ks0 to ks2 t inth t intl 0.8 v dd 0.2 v dd figure 18-9 . input timing for external interrupts and quasi-interrupts
ks57p3316 otp KS57C3316/p3316 18- 16 notes
electrical data KS57C3316/p3316 17- 2 table 17-1. absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? - 0.3 to + 6.5 v input voltage v in applies to all i/o ports - 0.3 to v dd + 0.3 output voltage v o ? - 0.3 to v dd + 0.3 output current high i oh one i/o port active - 15 ma all i/o ports active -30 output current low i ol one i/o port active + 30 (peak value) + 15 (note) total value for output ports + 100 (peak value) + 60 * operating temperature t a - 40 to + 85 c storage temperature t stg - 65 to + 150 note: the values for output current low ( i ol ) are calculated as peak value duty .
KS57C3316/p3316 ele ctrical data 17- 3 table 17-2 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below 0.7 v dd ? v dd v v ih2 p0.2, p1, p4.0, p4.2, p5, p6, ce and reset 0.8 v dd v dd v ih3 x in , x out , xt in , and xt out v dd ?0.1 v dd input l ow v oltage v il1 all input pins except those specified below ? ? 0.3 v dd v il2 p0.2, p1, p4.0, p4.2, p5, p6, ce and reset 0.2 v dd v il3 x in , x out , xt in , and xt out 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v , eo; i oh = ? 1 ma v dd ?2.0 ? v dd v oh2 v dd = 4.5 v to 5 . 5 v ; other output ports; i oh = ? 1 ma v dd ?1 .0 v dd output low voltage v ol1 v dd = 4.5 v to 5.5 v , eo; i ol = 1 ma , ? ? 2.0 v ol2 v dd = 4.5 v to 5.5 v other output ports; i ol = 10 ma ? ? 2 input h ig h leakage c urrent (note) i lih v in = v dd all input pins ? ? 3 m a input low leakage c urrent (note) i lil v in = 0 v all input pins ? ? - 3 output h igh l eakage c urrent (note) i loh v out = v dd all output pins ? ? 3 note: except for x in , x out , xt in and xt out .
electrical data KS57C3316/p3316 17- 4 table 17-2 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units v lc0 output voltage v lc0 t a = 25 c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2 com output voltage deviation v dc v dd = 5v, (v lc0 - com i i = 0 - 3 ) io = 15 m a (i = 0 - 3) ? 45 120 mv seg output voltage deviation v ds v dd = 5v, (v lc0 - com i i = 0 - 3 ) io = 15 m a (i = 0 - 3) 45 120 lcd output voltage deviation r lcd t a = 25 c 70 100 150 k w oscillator feed back resistors r osc1 v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0 v 300 600 1500 r osc2 v dd = 5.0 v, t a = 25 c xt in = v dd , xt out = 0 v 1500 3000 4500 pull-down resistor r d v dd = 5.0 v, v in = v dd ; vcofm, vcoam, amif, and fmif 15 30 45 pll-up resistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 4, 5, and 6 25 47 100 v dd = 3 v 50 95 200 r l2 v in = 0 v; v dd = 5 v reset 100 220 400 v dd = 3 v 200 450 800
KS57C3316/p3316 ele ctrical data 17- 5 table 17-2 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd 1 (2) main operating, pll operating: pcon = 0011b, scmod = 0000b ce = v dd ; crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.5 mhz ? 5.5 27 ma i dd 2 (2) ce low, 6.0 mhz ? 3.5 8 pcon = 0011b, scmod = 0000b ce = 0 v crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.5 mhz 2.5 5.5 v dd = 3 v 10% 6.0 mhz 1.6 4 4.5 mhz 1.2 3 i dd 3 ( 2 ) main i dle mode , 6.0 mhz ? 1.0 2.5 pcon = 0111b, scmod =0000b c rystal oscillator c1 = c2 = 22 pf v dd = 5 v 10 % 4.5 mhz 0.9 2.0 v dd = 3 v 10% 6.0 mhz 0.5 1.0 4.5mhz 0.4 0.8 i dd 4 (2) sub operating mode: pcon = 0011b, scmod = 1001b ce = 0 v; v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ua i dd 5 (2) sub i dle mode: pcon = 0111b, scmod = 1001b ce = 0 v; v dd = 3 v 10% 32 khz crystal oscillator ? 6 15 i dd6 (2) stop mode: cpu = fxt/4, scmod = 1101b ce = 0 v; v dd = 5 v 10% ? 0.5 3 i dd 7 (2) stop mode: cpu = fx/4, scmod = 0100b v dd = 5 v 10% ? notes: 1. supply current does not include current drawn through internal pull-up resistors and lcd voltage dividing resistors. 2 . data includes the power consumption for sub - system clock oscillation.
electrical data KS57C3316/p3316 17- 6 table 17-3 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
KS57C3316/p3316 ele ctrical data 17- 7 table 17-4 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillato r clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs.
electrical data KS57C3316/p3316 17- 8 table 17-5 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f clk = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf table 17-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.3 64 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0 ? k s2 10 reset and ce input low width t rsl input 10 1 ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx x as assigned by the imod0 register setting. table 17-6 . a.c. electrical characteristics ( continued) (t a = ? 1 0 c to + 70 c, v dd = 3.5 v to 5 . 5 v) parameter symbol conditions min typ max units a/d converting resolution ? ? ? 8 ? bits absolute accuracy ? ? ? ? 2 lsb ad conversion time t con ? 17 34/fxx (note) ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an v dd = 5 v 2 1000 ? m w note: fxx stands for the system clock ( fx or fxt).
KS57C3316/p3316 ele ctrical data 17- 9 table 17-6. a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c , v dd = 2.5 v to 3.5 v or v dd = 4.0 v to 5.5 v) parameter symbol conditions min typ max units vcofm, vcoam, fmif and amif input voltage (peak to peak) v in sine wave input 0.3 ? v dd v frequency fv coam vcoam mode, sine wave input; v in = 0.3v p-p 0.5 ? 30 mhz fv cofm vcofm mode, sine wave input; v in = 0.3v p-p 30 150 f amif amif mode, sine wave input; v in = 0.3v p-p 0.1 1.0 f fmif fmif mode, sine wave input; v in = 0.3v p-p 5 15
electrical data KS57C3316/p3316 17- 10 table 17-6 . a.c. electrical characteristics (concluded) (t a = ? 4 0 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s v dd = 1.8 v to 5.5 v 1.3 ? 64 with subsystem clock ( fxt) 114 122 125 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 tcl0 input high, low width t tih , t til v dd = 2.7. v to 5.5 v 0.48 ? ? m s v dd = 1.8. v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 650 v dd = 1.8 v to 5.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v external sck source 400 ? ? internal sck source t kcy /2- 50 v dd = 1.8 v to 5.5 v external sck source 1600 internal sck source t kcy /2-150 si setup time to t sik external sck source 100 ? ? sck high internal sck source 150 si hold time to t ksi external sck source 400 ? ? sck high internal sck source 400 output delay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 note: u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source.
KS57C3316/p3316 ele ctrical data 17- 11 1.5 mhz cpu clock 750 khz 15.6 khz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 250 khz 1.0475 mhz 1 mhz when pll/ifc operation, operating voltage range is 2.5 v to 3.5 v or 4.0 v to 5.5 v. main oscillator frequency 6 mhz 4.19 mhz 3 mhz 400 khz figure 17-1 . standard operating voltage range table 17-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 1 m a
electrical data KS57C3316/p3316 17- 12 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 17-2 . stop mode release timing when initiated b y reset execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 17-3 . stop mode release timing when initiated b y an interrupt request
KS57C3316/p3316 ele ctrical data 17- 13 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 17-4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 17-5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 17-6 . clock timing measurement at xt in
electrical data KS57C3316/p3316 17- 14 reset t rsl 0.2 v dd figure 17-7 . input timing for reset signal int0, 1, 2, 4, ks0 to ks2 t inth t intl 0.8 v dd 0.2 v dd figure 17-8 . input timing for external interrupts and quasi-interrupts
KS57C3316/p3316 mechanical data 18- 1 18 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table 80-qfp-1420c #80 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 0.80 0.35 + 0.10 note : dimensions are in millimeters. 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 figure 18-1. 80 -qfp-14 20c package dimensions
KS57C3316/p3316 ks5 7p3316 otp 19- 1 1 9 ks57p3316 otp overview the ks57p3316 single-chip cmos microcontroller is the otp (one time programmable) version of the KS57C3316 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the ks57p3316 is fully compatible with the KS57C3316, both in function and in pin configuration. because of its simple programming requirements, the ks57p3316 is ideal for use as an evaluation chip for the KS57C3316.
ks57p3316 otp KS57C3316/p3316 19- 2 p4.1/so p4.2/si p4.3/clo p5.0/adc0 p5.1/adc1 p5.2/adc2 p5.3/adc3 p6.0/ks0 p6.1/ks1 sdat /p6.2/ks2 sclk /p6.3/ks3 v dd /v dd 0 v ss /v ss 0 x out x in v pp /test xt in xt out reset / reset bias v lc 0 v lc 1 v lc 2 com0 v dd 1 e0 ce p3.0 p3.1 p3.2 p3.3 p0.0/btco p0.1/tclo0 p0.2/tcl0 p0.3/buz p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p4.0/ sck seg12/p10.0 seg11/p9.3 seg10/p9.2 seg9/p9.1 seg8/p9.0 seg7/p8.3 seg6/p8.2 seg5/p8.1 seg4/p8.0 seg3/p7.3 seg2/p7.2 seg1/p7.1 seg0/p7.0 com3 com2 com1 fmif amif v ss 1 vcoam vcofm p2.3 p2.2 p2.1 p2.0 seg27/p13.3 seg26/p13.2 seg25/p13.1 seg24/p13.0 seg23/p12.3 seg22/p12.2 seg21/p12.1 seg20/p12.0 seg19/11.3 seg18/p11.2 seg17/p11.1 seg16/p11.0 seg15/p10.3 seg14/p10.2 seg13/p10.3 ks57p3316 (80-qfp top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 figure 19-1. ks57p3316 pin assignments (80-qfp)
KS57C3316/p3316 ks5 7p3316 otp 19- 3 table 19-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p6.2 sdat 10 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input or push-pull output port. p6.3 sclk 11 i/o serial clock pin. input only pin. test v pp (test) 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. reset reset 19 i chip initialization v dd / v ss v dd / v ss 12/13 i logic power supply pin. v dd should be tied to +5 v during programming. table 19-2. comparison of ks57p3316 and KS57C3316 features characteristic ks57p3316 KS57C3316 program memory 16k bytes eprom 16k bytes mask rom operating voltage (v dd ) 1.8 v to 5.5 v 2.5 v to 3.5 v or 4.0 v to 5.5 v at pll/ifc operation 1.8 v to 5.5 v 2.5 v to 3.5 v or 4.0 v to 5.5 v at pll/ifc operation otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 80 qfp 80 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the vpp (test) pin of the ks57p3316, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 19-3. operating mode selection criteria v dd vpp(test) reg/ mem address(a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
ks57p3316 otp KS57C3316/p3316 19- 4 table 19-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below 0.7 v dd ? v dd v v ih2 p0.2, p1, p4.0, p4.2, p5, p6, ce and reset 0.8 v dd v dd v ih3 x in , x out , xt in , and xt out v dd ?0.1 v dd input l ow v oltage v il1 all input pins except those specified below ? ? 0.3 v dd v il2 p0.2, p1, p4.0, p4.2, p5, p6, ce and reset 0.2 v dd v il3 x in , x out , xt in , and xt out 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v , eo; i oh = ? 1 ma v dd ?2.0 ? v dd v oh2 v dd = 4.5 v to 5 . 5 v ; other output ports; i oh = ? 1 ma v dd ?1.0 v dd output low voltage v ol1 v dd = 4.5 v to 5.5 v , eo; i ol = 1 ma , ? ? 2.0 v ol2 v dd = 4.5 v to 5.5 v other output ports; i ol = 10 ma ? ? 2 input h igh leakage c urrent (note) i lih v in = v dd all input pins ? ? 3 m a input low leakage c urrent (note) i lil v in = 0 v all input pins ? ? ? 3 output h igh l eakage c urrent (note) i loh v out = v dd all output pins ? ? 3 output l ow l eakage c urrent (note) i lol v o ut = 0 v all output pins ? ? ? 3 note: except for x in , x out , x t in , and x t out
KS57C3316/p3316 ks5 7p3316 otp 19- 5 table 19-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units v lc0 output voltage v lc0 t a = 25 c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2 com output voltage deviation v dc v dd = 5v, (v lc0 - com i i = 0 - 3 ) io = 15 m a (i = 0 - 3) ? 45 120 mv seg output voltage deviation v ds v dd = 5v, (v lc0 - com i i = 0 - 3 ) io = 15 m a (i = 0 - 3) 45 120 lcd output voltage deviation r lcd t a = 25 c 70 100 150 k w oscillator feed back resistors r osc1 v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0 v 300 600 1500 r osc2 v dd = 5.0 v, t a = 25 c xt in = v dd , xt out = 0 v 1500 3000 4500 pull-down resistor r d v dd = 5.0 v, v in = v dd ; vcofm, vcoam, amif, and fmif 15 30 45 pull-up resistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 4, 5, and 6 25 47 100 v dd = 3 v 50 95 200 r l2 v in = 0 v; v dd = 5 v reset 100 220 400 v dd = 3 v 200 450 800
ks57p3316 otp KS57C3316/p3316 19- 6 table 19-4 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd 1 (2) main operating: pcon = 0011b, scmod = 0000b ce = v dd ; crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.5 mhz ? 5.5 27 ma i dd 2 (2) ce low mate: 6.0 mhz ? 3.5 8 pcon = 0011b, scmod = 0000b ce = 0 v crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.5 mhz 2.5 5.5 v dd = 3 v 10% 6.0 mhz 1.6 4 4.5 mhz 1.2 3 i dd 3 ( 2 ) main i dle mode : 6.0 mhz ? 1.0 2.5 pcon = 0111b, scmod =0000b c rystal oscillator c1 = c2 = 22 pf v dd = 5 v 10 % 4.5 mhz 0.9 2.0 v dd = 3 v 10% 6.0 mhz 0.5 1.0 4.5mhz 0.4 0.8 i dd 4 (2) sub operating mode: pcon = 0011b, scmod = 1001b ce = 0 v; v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ua i dd 5 (2) sub i dle mode: pcon = 0111b, scmod = 1001b ce = 0 v; v dd = 3 v 10% 32 khz crystal oscillator ? 6 15 i dd6 (2) stop mode: cpu = fxt/4, scmod = 1101b ce = 0 v; v dd = 5 v 10% ? 0.5 3 i dd 7 (2) stop mode: cpu = fx/4, scmod = 0100b v dd = 5 v 10% ? notes: 1. supply current does not include current drawn through internal pull-up resistors and lcd voltage dividing resistors. 2 . data includes the power consumption for sub - system clock oscillation.
KS57C3316/p3316 ks5 7p3316 otp 19- 7 table 19-5 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
ks57p3316 otp KS57C3316/p3316 19- 8 table 19-6 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillato r clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs.
KS57C3316/p3316 ks5 7p3316 otp 19- 9 table 19-7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f clk = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf table 19-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.3 64 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0 ? k s2 10 reset and ce input low width t rsl input 10 1 ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx x as assigned by the imod0 register setting. table 19-8 . a.c. electrical characteristics ( continued) (t a = ? 1 0 c to + 70 c, v dd = 3.5 v to 5 . 5 v) parameter symbol conditions min typ max units a/d converting resolution ? ? ? 8 ? bits absolute accuracy ? ? ? ? 2 lsb ad conversion time t con ? 17 34/fxx (note) ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an v dd = 5 v 2 1000 ? m w note: fxx stands for the system clock (fx or fxt).
ks57p3316 otp KS57C3316/p3316 19- 10 table 19-8. a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c , v dd = 2.5 v to 3.5 v or v dd = 4.0 v to 5.5 v) parameter symbol conditions min typ max units vcofm, vcoam, fmif and amif input voltage (peak to peak) v in sine wave input 0.3 ? v dd v frequency fv coam vcoam mode, sine wave input; v in = 0.3v p-p 0.5 ? 30 mhz fv cofm vcofm mode, sine wave input; v in = 0.3v p-p 30 150 f amif amif mode, sine wave input; v in = 0.3v p-p 0.1 1.0 f fmif fmif mode, sine wave input; v in = 0.3v p-p 5 15
KS57C3316/p3316 ks5 7p3316 otp 19- 11 table 19-8 . a.c. electrical characteristics ( continued) (t a = ? 4 0 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s v dd = 1.8 v to 5.5 v 1.3 ? 64 with subsystem clock (fxt) 114 122 125 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 tcl0 input high, low width t tih , t til v dd = 2.7. v to 5.5 v 0.48 ? ? m s v dd = 1.8. v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 650 v dd = 1.8 v to 5.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v external sck source 400 ? ? internal sck source t kcy /2- 50 v dd = 1.8 v to 5.5 v external sck source 1600 internal sck source t kcy /2-150 si setup time to t sik external sck source 100 ? ? sck high internal sck source 150 si hold time to t ksi external sck source 400 ? ? sck high internal sck source 400 output delay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 note: u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source.
ks57p3316 otp KS57C3316/p3316 19- 12 1.5 mhz cpu clock 750 khz 15.6 khz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 250 khz 1.0475 mhz 1 mhz when pll/ifc operation, operating voltage range is 2.5 v to 3.5 v or 4.0 v to 5.5 v. main oscillator frequency 6 mhz 4.19 mhz 3 mhz 400 khz figure 19-2 . standard operating voltage range table 19-9 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 1 m a
KS57C3316/p3316 ks5 7p3316 otp 19- 13 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 19-3 . stop mode release timing when initiated b y reset execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 19-4 . stop mode release timing when initiated b y an interrupt request
ks57p3316 otp KS57C3316/p3316 19- 14 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 19-5 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 19-6 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 19-7 . clock timing measurement at xt in
KS57C3316/p3316 ks5 7p3316 otp 19- 15 reset t rsl 0.2 v dd figure 19-8 . input timing for reset signal int0, 1, 2, 4, ks0 to ks2 t inth t intl 0.8 v dd 0.2 v dd figure 19-9 . input timing for external interrupts and quasi-interrupts
ks57p3316 otp KS57C3316/p3316 19- 16 notes

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